Lattice Expands Power Management Mixed-Signal PLD Family; Second Member of Revolutionary ispPAC Power Manager Family Released with Enhanced Specifications

HILLSBORO, Ore.--(BUSINESS WIRE)--May 5, 2003--Lattice Semiconductor Corporation, (Nasdaq:LSCC), the industry's leading supplier of in-system programmable devices, today extended its revolutionary ispPAC(R) Power Manager mixed-signal family with the production release of its Power604 device. The Power604 device, like its predecessor the Power1208, provides a complete solution for printed circuit board (PCB) power sequencing and management through an optimized set of programmable digital and analog functions. The streamlined architecture of the Power604 provides extremely cost-effective power management control in a compact 44-pin Thin Quad Flat Pack (TQFP) package.

The complexity of power supply management has increased dramatically in recent years as the number of voltages found on the typical PCB has risen sharply. In addition, most system-level integrated circuits, whether processors, ASSPs, ASICs or FPGAs, have device-specific power supply sequencing and tracking requirements that make each PCB power supply management design unique. Traditional approaches, consisting of arcane collections of resistors, capacitors, discrete analog and logic functions, are no longer practical solutions.

Lattice's Power Manager devices provide a standard, off-the-shelf programmable mixed-signal solution for power management that enhances reliability and speeds time-to-market. Analog features such as input comparator thresholds and digital functions such as supply control sequences are programmed into non-volatile E2CMOS(R) elements on the devices using an IEEE1149.1 boundary scan protocol. The Power604 features 6 precision analog threshold comparators with on-chip programmable voltage references for supply monitoring, 4 noise-immune digital inputs and 4 open-drain digital outputs for system control interfacing, 2 programmable timers with an on-chip 250 kHz oscillator for delay control and an 8 macrocell Complex PLD (CPLD) to implement sequencing and control functions. With the production release of the Power604, analog input threshold accuracy, a key parameter when monitoring voltage levels, has been further improved to 0.9% from 1.2%. In addition, the device has been ruggedized to operate reliably in noisy power supply environments from 2.25V to 5.5V.

"The complexity of the power management functions found on the typical PCB has escalated enormously due to the wide variation in the number of supplies and types of devices found on a given board," said Stan Kopec, vice president of corporate marketing. "With the addition of the Power604 device, pin-compatible with the Power1208, designers can now standardize their power management approach across all their PCBs and use our PC-based design software to select the most appropriate device and program exactly the functionality needed into it."

Applications for Power Manager devices span all types of electronic equipment, including telecom and networking systems, storage systems, servers, test equipment and automotive electronics. Their programmable features make them ideal for controlling multiple power supplies in conjunction with a wide range of regulator and switching technologies. Together with N-channel switching FETs, LDO (Low Drop Out) regulators, and/or DC-DC convertors (power bricks), the Power1208 and Power604 devices provide compact, flexible power supply control solutions.

Power Manager Design Support in PAC-Designer(R) Version 2.1

Power supply sequencing and monitoring designs can be implemented in ispPAC devices using Lattice's latest PAC-Designer software version 2.1. The PAC-Designer software is an intuitive schematic design entry and simulation tool. Complex sequencing and monitoring functionality can be efficiently designed through easy-to-use pull-down menus in PAC-Designer's LogiBuilder(TM) module. The latest version of the tool also features a new Supervisory Logic window entry mechanism to facilitate control output specification. Designs can be completely verified using the tool's built-in waveform simulator. The PAC-Designer software is available for download from Lattice at www.latticesemi.com.

The PACsystemPOWR development tool was developed to enable designers to build quick prototypes of their circuit implementations in order to verify functionality. Designs implemented using PAC-Designer are downloaded into the device through a serial ispDOWNLOAD(R) cable that connects to a PC's parallel port. The tool contains an evaluation board for an ispPAC Power Manager device, an ispDOWNLOAD cable, and the PAC-Designer v2.1 software.

Price and Availability

Prices for the Power604 device start at $5.95 in 10,000 piece quantities. The device in a 44-pin TQFP package (Industrial temperature grade, -40 degrees C to +85 degrees C is available immediately. The ordering part number is ispPAC-POWR604-01T44I.

PACsystemPOWR evaluation kits are also available through authorized Lattice distributors or on the Lattice web site at a price of $149.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGAs), Field Programmable System Chips (FPSCs) and high-performance ISP(TM) programmable logic devices (PLDs). Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), in-system programmable, E2CMOS, ispPAC, PAC-Designer, ispDOWNLOAD, LogiBuilder, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

CONTACT: Lattice Semiconductor Corporation
             Sean Hildenbrand, PR, 503/268-8680
             Sean.hildenbrand@latticesemi.com